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Our Projects



Standard Cell Library Development

Design a comprehensive standard cell library (300 cells with different VT and drive strengths) containing a variety of logic gates and essential functional blocks for digital circuit design

Create high-quality layout designs for each standard cell, adhering to the foundry’s design rules and guidelines. Create an accurate library with multiple cell variants to support critical parameters like area, delay, power, and noise.

Perform layout verification using Design Rule Check (DRC) and Layout vs. Schematic (LVS) tools to ensure the cells meet the manufacturing requirements.

Implement robust power and ground distribution networks to ensure reliable power delivery to all cells. Strategically develop power and ground distribution networks to enable efficient and reliable power delivery across the library.

Integrate low-power variants of standard cells to provide support for power-sensitive applications, contributing to enhanced power efficiency.

Produce comprehensive documentation detailing the design process, layout guidelines, and cell specifications for easy understanding and future use.

Effectively present the project’s outcomes to peers and collaborate with team members to achieve project objectives efficiently.



ALU Design Using Standard Cell Library

Design a fully functional Arithmetic Logic Unit (ALU) capable of performing various arithmetic and logical operations.

Define the ALU’s supported operations, such as addition, subtraction, multiplication, AND, OR, XOR, shift, and compare.

Determine the ALU architecture, including the number of input and output ports, bit-width, and the internal organization of the ALU.

Choose an appropriate standard cell layout library with cells that meet the required performance and power specifications.

Create a detailed design specification, outlining the ALU’s behavior, functionality, and interfaces.

Map the logic functions of the ALU to the selected standard cell library, selecting appropriate cells for each operation.

Develop the layout for each ALU component, ensuring adherence to design rules and guidelines of the standard cell library.

Integrate individual ALU components into a complete ALU design, ensuring proper connectivity and signal flow.

Perform DRC and LVS checks on the ALU layout to ensure its correctness and compliance with the foundry’s rules.

Verify the ALU’s functionality by simulating various test cases and comparing the results against expected outputs.

Estimate the area occupied by the ALU in terms of the number of standard cells used.


Opamp Design

Implement the schematic and layout of the op-amp, which consist of PMOS and NMOS current mirrors, NMOS differential pairs, and an inverter amplifier at the output stage.

Implement current mirror layouts using the inter-Digitization Matching technique.

Implement current mirror layouts using the inter-Digitization Matching technique.

Use dummy devices to ensure that each device in the matching pattern has the same geometry when etched in silicon, and use a guard ring to avoid latch-up.

Design layouts in layout XL by generating the instances from the schematic.

Place vias wherever required to obtain a better yield, and use wider metals for global nets.

Plan an efficient floorplan, execute appropriate routing, and hence optimize the area greatly.


Bandgap Reference Circuit (BGR)

A bandgap voltage reference is a temperature-independent voltage reference circuit widely used in integrated circuits. It produces a fixed voltage regardless of power supply variations or temperature changes.

Design, simulate, and analyse PTAT and CTAT circuits individually, and then integrate them to design a BGR

Implement a cascode current mirror for better CTAT control.

A bell curve of 1.3 mV can be observed for a constant output voltage of 2.3 volts.

Protect the resistor bank with a guard ring since resisters are high-noise devices.


Phase Locked Loop (PLL)

The Phase-locked loop (PLL) is used to generate stable and accurate frequencies and also stable signals.

Blocks that make up this PLL are the phase frequency detector (PFD), Charge Pump (CP), loop filter, ring oscillator, and frequency divider.

Implement a simple DFF+AND-based PFD for minimum complexity and minimum power consumption. Two TSPC (True Single-Phase Clocking) D-FF are used, and a symmetric NAND along with a NOT gate is used as feedback.

The three states of the PFD are used to regulate a charge pump, which is an electronic switch with three positions. The switch sends a current to the loop filter as a control signal.

A loop filter converts the pulsating DC output of the CP to a smooth control voltage that can be fed to the oscillator.

A frequency divider divides the input frequency by N based on the number of stages..

Implement a 5-stage frequency divider.

PLL has a 700ns lock time and a 5MHz bandwidth.

Use matching techniques like Inter-Digitization and common centroid for Current mirrors and differential pairs of CP.

Optimize the floorplan by matching the heights of blocks and devices.


4-Bit Flash Analog to Digital Converter (ADC)

Flash ADC, also known as parallel ADC, is a type of Analog-to-Digital Converter (ADC) that uses a bank of comparators to directly convert an analogue input voltage into a digital output.

The flash ADC is known to be the fastest ADC.

The designed ADC consists of A resistor bank, comparator opamp, thermometer encoder made of transmission gate-based multiplexers, and a buffer stage.

Flash ADCs use a resistor bank consisting of 2N resistors to achieve N-bit resolution.

If the positive input of the comparator is at a greater potential than the negative input, the output of the comparator is a logic 1, whereas if the + input is at a lower potential than the – input, The output of the comparator is at a logic A typical Flash ADC uses 2N – 1..

This ADC can operate at a 20 MHz frequency

A buffer stage is added at the output of the encoder to get a proper voltage swing..

Resistors routing is done by matching each and every node’s connection. Matching net connections for critical signals.

Tapping of vias to power nets is done periodically for all the subblocks in the top level in order to ensure proper power distribution and signal integrity.


Custom SRAM Instance

Design a single-port 6T SRAM (HD) Bit-Cell.

Understand the workings of a Bit-cell (read/Write operation) and the structure of the memory architecture.

Characterization of 6T-SRAM (Single-port) bit cells by varying Temperature and Supply voltage

Schematic and Layout Design of Peripheral Circuits: 32×32 Bit-Cell Array, Row Decoder, Column IO, and Control Block

A precharge mux, latch-based Sense amplifier, and I/O latch are designed.

Designed a control block with very strict time constraints to enable proper functionality.

Functional Verification of successful read and write operations

Bit-Cell Layout using the Half-Cell Approach

Design edge cells to avoid abrupt endings in the bit-Cell array.

The layout of the Row Decoder is designed by considering the height of 4-Bit Cells.

The Sense Amplifier layout is designed with analogue layout concepts such as common centroid symmetry and a guard ring to prevent latch-up.

Design Control Block layouts using Standard Cells.