Courses
Full Time VLSI Layout Design Course
Three months per Module, Online, Mentors from top VLSI Companies
- The syllabus is designed to holistically cover all the possible domains in Layout design and maximize the placement opportunities for students.
- Mentors with over a Decade of semiconductor Expertise in Analog ASICs and Memory Design. Curriculum with right blend of Theory Labs and Current Industry Trends.
- Designed and delivered by the Semiconductor Experts.
- Direct access to the mentorship/counselling by VLSI professionals in Intel, Qualcomm, IBM, Synopsys, ARM.
Bridge Course
This course is a complementary module and is mandatory for all the enrolled students. Some of the topics are self driven with constant evaluation. This helps as pre requisite for the other modules.
Standard Cell Layout Design
Standard cells are well defined and pre-characterized cells used in ASIC Design flow as basic building blocks. All these cells are equal in height and can easily fit into the standard cell row. Standards cells are highly reusable and save lots of ASIC design time
Analog Layout Design
Analog design in the context of integrated circuit (IC) design is a discipline that focuses on the creation of circuits that operate in and are optimized for continuous time-domain behavior.
Memory Compiler Layout Design
Memory is ubiquitous. Compute-intense applications such as cloud-based high-performance computing (HPC), big data analytics, machine learning (ML), and advanced driver assistance systems (ADAS) in modern cars demand large and fast memory resources to perform as expected.
Placement Assistance
Placement support offers career assistance and guides students in finding suitable employment opportunities, and prepares them for job interviews. Placement support also aids in network development and resumes building for students.
Bridge Course
- RC Circuits, Network Analysis
- Microelectronic Basics, Device Physics
- MOS Basics, Fabrication, Diodes, BJT
- Advance Topics (Finfets, Double Patterning)
- Tool trainings, schematics, simulations
- Stick diagrams, Layout design, LVS, DRC
- QA: EM, IR, Antenna, Density, ERC, Latchup, Shielding, Matching, Sheer Resistance, LoD, WPE, DFM
- PVT Corners, Hierarchical and Flat Layouts
- Logic Design Basics
- File formats: GDS, CDL, LEF, .LIB
Standard Cell Layout Design
- ASIC Design Flow
- Role of standard cell libraries in IC design
- Introduction to Standard Cell Architecture
- Introduction to concepts: Grids, Hit-points, Half-DRC, PnR, Fanout, Drive Strength, Tapless Library
- Circuit and Layout of Std. Cell Library (Inv, Nand, Nor, Flops, Latches, Delay cells, Fillers)
- Floorplanning, Power planning, LVS, DRC
- Introduction to Standard Cell Characterization (timing, setup/hold, power, leakage), Files (LEF/DEF, GDS, CDL, Liberty)
- Hands-on projects involving standard cell layout: ALU
- Assignments, Tests, Presentations
- Projects
Analog Layout Design
- Analog Design Flow
- Analog v/s Digital Layouts
- Concepts of Matching, Guardring, Shielding
- Circuit and Layout Design of Resistors, Capacitors, Current Mirrors, Opamp
- Circuit and layout Design of ADC/DAC/PLL
- Assignments, Test, Presentations
- Projects
Memory Layout Design
- Introduction to Memory Architecture and Hierarchy. Importance of Embedded Memories in SoCs
- 6T SRAM Cell Structure, Read Write Operations, SNM, RNM and other Stability Analysis
- Array Design, Bitcell Transistor Sizing, Corner and Edge Cells
- Circuit and Layout Design of IO: Column Mux, Precharge, Sense Amplifier, Latches, Drivers
- Circuit and Layout Design of Rowdrivers: Predecs and Final Drivers, Programming Techniques for Decoding
- Control Block Design and Layout
- Full Instance Circuit Simulation for Functionality, Layout Design, LVS and DRC.
- Introduction to Memory Compilers
- Assignments, Test, Presentations
- Projects
Placement Assistance & Course Highlights
- Resume Preparation, Review and Mock Interviews
- Group Discussions, Presentations
- Sourcing Resume Across VLSI Companies
- Course and Internship Certification
- Placement assistance till the candidate is placed