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Our Courses

Three months per Module, Online, Mentors from top VLSI Companies
  • Mentors with over a Decade of semiconductor Expertise in Analog ASICs and Memory Design.
  • Designed and delivered by the Semiconductor Experts.
  • Direct access to the mentorship/counselling by VLSI professionals in Intel, Qualcomm, IBM, Synopsys, ARM.
  • The syllabus is designed to holistically cover all the possible domains in Layout design and maximize the placement opportunities for students.



  • Bridge Course

    RC Circuits, Network Analysis

    Microelectronic Basics, Device Physics.

    MOS Basics, Fabrication, Diodes, BJT

    Advance Topics (Finfets, Double Patterning)

    Tool trainings, schematics, simulations.

    Stick diagrams, Layout design, LVS, DRC QA: EM, IR, Antenna, Density, ERC, Latchup,.

    Shielding, Matching, Sheer Resistance, LoD, WPE, DFM.

    PVT Corners, Hierarchical and Flat Layouts

    Logic Design Basics.

    Logic Design Basics.



    Standard Cell Layout Design

    ASIC Design Flow

    Role of standard cell libraries in IC design .

    Introduction to Standard Cell Architecture.

    Introduction to concepts: Grids, Hit-points, Half-DRC, PnR, Fanout, Drive Strength, Tapless Library Circuit and Layout of Std. Cell Library (Inv, Nand, Nor, Flops, Latches, Delay cells, Fillers).

    Floorplanning, Power planning, LVS, DRC Introduction to Standard Cell Characterization (timing, setup/hold, power, leakage), Files (LEF/DEF, GDS, CDL, Liberty).

    Hands-on projects involving standard cell layout: ALU Assignments, Tests, Presentations.


    Analog Layout Design

    Analog Design Flow

    Analog v/s Digital Layouts

    Concepts of Matching, Guardring, Shielding Circuit and Layout Design of Resistors, Capacitors, Current Mirrors, Opamp

    Circuit and layout Design of ADC/DAC/PLL

    Assignments, Test, Presentations


    Memory Layout Design

    Introduction to Memory Architecture and Hierarchy. Importance of Embedded Memories in SoCs.

    6T SRAM Cell Structure, Read Write Operations, SNM, RNM and other Stability Analysis.

    Array Design, Bitcell Transistor Sizing, Corner and Edge Cells

    Circuit and Layout Design of IO: Column Mux, Precharge, Sense Amplifier, Latches, Drivers Circuit and Layout Design of Rowdrivers: Predecs and Final Drivers, Programming Techniques for Decoding.

    Control Block Design and Layout Full Instance Circuit Simulation for Functionality, Layout Design, LVS and DRC.

    Introduction to Memory Compilers

    Assignments, Test, Presentations.


    Placement Assistance & Course Highlights

    Resume Preparation, Review and Mock Interviews

    Group Discussions, Presentations.

    Sourcing Resume Across VLSI Companies

    Course and Internship Certification

    Placement assistance till the candidate is placed